VRAM access speed
This page was last modified 16:37, 10 January 2022 by NYYRIKKI. Based on work by Gdx.

Please note: This borderline information is based on hearsay. Use at your own risk.

In most cases MSX programmer does not need to think about speed while accessing VRAM since typically the minimum wait time between VRAM accesses is equal to 13 Z80 clock cycles (@3.58MHz) while typical I/O instruction on MSX takes 12 cycles + two M1-waitstates, so total 14 cycles.

There are anyway few exceptions and things you need to know:

  • When SCREEN 1, 2 or 3 is used on TMS99x8 the minimum wait time is 29 cycles
  • When SCREEN 0, WIDTH 80 text mode is used on V99x8 the minimum wait time is 20 cycles
  • When VRAM address is set up for read on V99x8 the minimum time before first read can be done is 10 cycles.
  • On R800 CPU programmer does not need to wait ever because S1990 automatically fixes the wait to 62 cycles. (@7MHz)
  • Some machines add one extra cycle to VDP I/O while others don't
  • On V9958 it is possible to enable automatic waitstate insertion.

Even when operating in slower display mode, the VRAM can be accessed "full speed" while VDP is drawing border or the screen output has been disabled.

While calculating needed delays, it is useful to know that the actual I/O is the very last thing I/O instructions do. For example in IN A,(n) and OUT (n),A instructions (12 cycles), the /IORQ signal is active in cycles 9-12 and on OUTI (18 cycles) the /IORQ signal is active in cycles 15-18.

Examples don'ts:

  • Do not read or write to VRAM directly after the VRAM address setting on MSX1. (Wait a little with 3 x NOP for example before send data to the VRAM)
  • Do not use OTIR nor INIR out of the Vblank to transfer data between RAM and VRAM on MSX1. Use OUTI/INI and JP PE,$-2 instead.