Description

This connector can be found on the Victor HC-90 and Victor HC-95 MSX2 computers.

Pinout

No.	Signal name	No.	Signal name	No.	Signal name
a1	GND	b1	GND	c1	+I2V
a2	JVCREQ	b2	CS1	c2	-12V
a3	JVCACK	b3	CS2	c3	SLOT
a4	BUSREQ	b4	BUSDIR	c4	N.C.
a5	BUSACK	b5	ME*	c5	N.C.
a6	RESET	b6	lOE	c6	RD
a7	ST	b7	LlR	c7	WR
a8	HALT	b8	INT01	c8	REF
a9	NMI	b9	INT1	c9	INT02
a10	E	b10	INTRET	c10	INT2
a11	Reserved	b11	WAIT	c11	A0
a12	Reserved	b12	A1	c12	A2
a13	Reserved	b13	A3	c13	A4
a14	Reserved	b14	A5	c14	A6
a15	Reserved	b15	A7	c15	A8
a16	Reserved	b16	A9	c16	A10
a17	Reserved	b17	AM	c17	A12
a18	Reserved	b18	A13	c18	A14
a19	Reserved	b19	A15	c19	A16
a20	Reserved	b20	A17	c20	A18
a21	Reserved	b21	D1	c21	D0
a22	Reserved	b22	D3	c22	D2
a23	TXAI	b23	D5	c23	D4
a24	RXAI	b24	D7	c24	D6
a25	RAMSEL	b25	CK0/DREQ0	c25	TXA0
a26	BUSCON	b26	DCD0	c26	RXA0
a27	CK1/TEND0	b27	RTS0	c27	DREQ1
a28	CKS	b28	CTS0	c28	TEND1
a29	RXS/CTS1	b29	+ 5V	c29	+5V
a30	TXS	b30	+ 5V	c30	+5V
a31	GND	b31	Ø	c31	2Ø
a32	GND	b32	GND	c32	GND

Signals

Signal name	Direction	Out/In	Description
D0 _D7	I/O	OUTIO IN 2	CPU data Pull up on bus 15KΩ
A0_A18	I/O	OUTIO IN 2	It enters an input state by BUS REQUEST from the outside. By default this is in an output state.
JVCREQ	I	OUT 5	By setting JVCREQ to JVC mode and booting up with an external boot ROM, JVCACK becomes 0 by setting bit 3 of the OFF 5H address of the I / O address to 1.
CS1	0	OUT5	Decode signal of PAGE 2 in MSX mode
CS2	0	OUT5	Decode signal of PAGE 3 in MSX mode
SLOT	0	OUT5	Decoding of the MSX mode signals >br>SLOT 2 is the slot in the bottom SLOT O,3 is connected to the top SLOT.
BUSDIR	I	IN4	Data - Direction of bus - Pull up with control signal 4.7KΩ. In the BUS REQUEST state, the switching direction is reversed
BUSREQ	I		Bus open to CPU - PULL UP with request signal 2.2 KΩ
BUSACK	0	OUT 5	Bus release from CPU - Response signal
RESET	O	OUT 3	RESET signal from main unit
RD	I/O	OUT 5 IN 2	CPU RD signal It switches to IN by BUS REQUEST, default is OUT
WR	I/O	OUT 5 IN 2	CPU WR signal Switch to IN with BUS REQUEST, default is OUT
ME	I/O	OUT 5 IN 2	ME signal of CPU (MREQ signal in Z80) Switch to IN with BUS REQUEST, default is OUT
IOE	I/O	OUT 5 IN 2	The CPU's IOE signal (IORLQ signal in Z80) Switch to IN with BUS REQUEST, default is OUT
LIR	I/O	OUT 5 IN 2	The LIR signal of the CPU (Ml signal in Z80) Switch to IN with BUS REQUEST, default is OUT
REF	I/O	OUT 5 IN 2	The CPU REF (RFSH signal in Z80) Switch to IN by BUS REQUEST, default is OUT
ST	O	OUT 2	ST signal of HD64B180 CPU
HALT	O	OUT 2	HALT signal of HD64B180 CPU
E	O	OUT 2	E signal of HD64B180CPU
INT01 INT02	I I		Interrupt request signal 1 PULL UP is done with 2.2KΩ. Interrupt request signal 2 PULL UP is done with 2.2KΩ.
NMI			Pull up with NMI request signal 4.7 KΩ
INT1 INT2	I I		PULL UP with 2.2 KΩ connected to INT 1 of HD64B180 connected to INT2 of HD64B180
INTRET	O	OUT3	It is connected to the INT of the CPU.
WAIT	I		INT RETURN signal when CPU is externally connected It is connected to WAIT of CPU. It is PULL UP by 1KΩ and it is wired OR.
RAMSEL	I		The internal RAM enable signal 1KΩ, PULL UP on the wired-OR.
BUSCON	I		Data - Tri-State bus - control In 1KΩ, PULL UP. In 1KΩ, PULL UP. Control enabled. With 0, data will flow.
CK0/DREQ0 TXAO RXAO TXA1 RXA1 RTS0 CTS0 CK1/TEND0 CKS TXS RXS/CTS1 DREQ1 TEND1	I/O O I O I I/O I/O O I I O	IN2 OUT2	There is no buffer connected to the HD64B180.
Ø	I/O	OUT4 IN2	CPU Clock output When BUS REQUEST for input is used, an external clock signal must be supplied.
2 Ø	0	OUT 5	Output with twice the CPU clock

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