Victor HC-90
This page was last modified 15:52, 23 August 2017 by Rderooy. Based on work by Sander and Mars2000you and others.

Contents

Description

The Victor HC-90 is a personal computer with two CPU made by JVC (Japan Victor Company) and released in 1986.

The HC-90 was aimed at the Japanese market and features a Japanese keyboard. It is available in light gray.

Official price: ¥168,000.

Brand Victor
Type HC-90
Year 1988
RAM 64kB
VRAM 128kB
Media MSX cartridge, 720kB 3,5" floppy diskette
Video Yamaha V9938
Audio PSG (AY-3-8910)
Chipset  ?
Extras Hardware: FDD drive, RS232C interface, second CPU HD64180, superimposition and frame grabber capacity, Kanji-ROM JIS level 1
Software: Title editor, Telop (television opaque projector), Wipe editor, etc

Pictures

Victor HC-90
Victor HC-90 front detail
Victor HC-90 back side

Specifications

The HC-90 is an MSX2 with two CPU, a Z80A processor from Zilog at 3.58 MHz and a Z180 (HD64180) at 6,144 MHz. A single CPU may be used at a time by manual switching. This switch must only be changed when the MSX is turned OFF because it also switches the Main-Rom and Sub-ROM.

By pressing <ESC> at boot, modes for activating the build-in RS232 interface, tweaking the IO wait states and DRAM refresh rate for the HD64180 "Turbo" mode.

The adresses 7FF8h~7FFFh of FDD controler and RS-232C Roms are used to control the I/O ports of floppy disk drives, RS-232C and system.

The HC-90 both feature on-board frame grabber and superimposing capabilities.

Different expansion cards exist:

  • IF-C40SK S-Video interface (in and out)
  • IF-C9C VHD Interface. With this interface you can connect the computer to a Victor VHD player through the AHD port. Compatible VHD players mark the VHDpc logo. Several games were made for this system.

The main RAM is present on slot 0-2, a configuration that can cause poorly written software to crash. Also, with this layout, the POKE-1,(15-PEEK(-1)\16)*17 trick to workaround buggy softwares that don't handle subslots properly will cause this machine to freeze.

Connections

  • RGB output (D-Sub25 connector)
  • RF output
  • Analog stereo sound & Composite video output
  • Analog stereo sound & Composite video input
  • Tape recorder connector
  • Keyboard connector
  • Centronics compatible Parallel port for a printer
  • RS-232C
  • 2 general connectors (joysticks, mouse, paddle controllers, ...)
  • One cartridge port at the front
  • 2 custom connectors of 96 pins for expansion card (inside)
  • 4 custom connectors of 40 pins for RAM, FDD controler, etc (inside)
  • AC power plug (for the monitor)

JVC Slot Layout

HC90-95 Slot layout.png

96-PIN JVC Slot Connector

96-pin connector jvc.png

96-PIN JVC Slot layout

No. Signal name No. Signal name No. Signal name
a1 GND b1 GND c1 + I2V
a2 JVCREQ b2 CS1 c2 -12V
a3 JVCACK b3 CS2 c3 SLOT
a4 BUSREQ b4 BUSDIR c4 N.C.
a5 BUSACK b5 ME* c5 N.C.
a6 RESET b6 lOE c6 RD
a7 ST b7 LlR c7 WR
a8 HALT b8 INT01 c8 REF
a9 NMI b9 INT1 c9 INT02
a10 E b10 INTRET c10 INT2
a11 Reserved b11 WAIT c11 A0
a12 Reserved b12 A1 c12 A2
a13 Reserved b13 A3 c13 A4
a14 Reserved b14 A5 c14 A6
a15 Reserved b15 A7 c15 A8
a16 Reserved b16 A9 c16 A10
a17 Reserved b17 AM c17 A12
a18 Reserved b18 A13 c18 A14
a19 Reserved b19 A15 c19 A16
a20 Reserved b20 A17 c20 A18
a21 Reserved b21 D1 c21 D0
a22 Reserved b22 D3 c22 D2
a23 TXAI b23 D5 c23 D4
a24 RXAI b24 D7 c24 D6
a25 RAMSEL b25 CKO/DREQO c25 TXA0
a26 BUSCON b26 DCDO c26 RXA0
a27 CKI/TENDO b27 RTSO c27 DREQI
a28 CKS b28 CTSO c28 TENDI
a29 RXS/CTSI b29 + 5V c29 +5V
a30 TXS b30 + 5V c30 +5V
a31 GND b31 Ø c31
a32 GND b32 GND c32 GND

JVC Slot Signals

Signal line name Input / output Out/In Description
D0 _D7 I/O OUTIO
IN 2
CPU data
Pull up on bus 15KΩ
A0_A18 I/O OUTIO
IN 2
It enters an input state by BUS REQUEST from

the outside. By default this is in an output state.

JVCREQ I OUT 5 By setting JVCREQ to JVC mode and booting up

with an external boot ROM, JVCACK becomes 0 by setting bit 3 of the OFF 5H address of the I / O address to 1.

CS1 0 OUT5 Decode signal of PAGE 2 in MSX mode
CS2 0 OUT5 Decode signal of PAGE 3 in MSX mode
SLOT 0 OUT5 Decoding of the MSX mode signals, SLOT 2 is the slot

in the bottom. SLOT O,3 is connected to the top SLOT.

BUSDIR I IN4 Data - Direction of bus

- Pull up with control signal 4.7KΩ.
In the BUS REQUEST state, the switching direction is reversed

BUSREQ I Bus open to CPU - PULL

UP with request signal 2.2 KΩ

BUSACK 0 OUT 5 Bus release from CPU -

Response signal

RESET O OUT 3 RESET signal from main unit
RD I/O OUT 5
IN 2
CPU RD signal
It switches to IN by BUS REQUEST, default is OUT
WR I/O OUT 5
IN 2
CPU WR signal
Switch to IN with BUS REQUEST, default is OUT
ME I/O OUT 5
IN 2
ME signal of CPU (MREQ signal in Z80)
Switch to IN with BUS REQUEST, default is OUT
IOE I/O OUT 5
IN 2
The CPU's IOE signal (IORLQ signal in Z80)
Switch to IN with BUS REQUEST, default is OUT
LIR I/O OUT 5
IN 2
The LIR signal of the CPU (Ml signal in Z80)
Switch to IN with BUS REQUEST, default is OUT
REF I/O OUT 5
IN 2
The CPU REF (RFSH signal in Z80)
Switch to IN by BUS REQUEST, default is OUT
ST O OUT 2 ST signal of HD64B180 CPU
HALT O OUT 2 HALT signal of HD64B180 CPU
E O OUT 2 E signal of HD64B180CPU
INT01
INT02
I
I
Interrupt request signal 1 PULL UP is done

with 2.2KΩ. Interrupt request signal 2 PULL UP is done with 2.2KΩ.

NMI Pull up with NMI request signal 4.7 KΩ
INT1
INT2
I
I
PULL UP with 2.2 KΩ

connected to INT 1 of HD64B180
connected to INT2 of HD64B180

INTRET O OUT3 It is connected to the INT of the CPU.
WAIT I INT RETURN signal when CPU is externally

connected It is connected to WAIT of CPU. It is PULL UP by 1KΩ and it is wired OR.

RAMSEL I The internal RAM enable signal 1KΩ, PULL UP on the wired-OR.
BUSCON I Data - Tri-State bus - control
In 1KΩ, PULL UP.
In 1KΩ, PULL UP.
Control enabled. With 0, data will flow.
CKO/DRQO
TXAO
RXAO
TXA1
RXA1
RTS0
CTS0
CK1/TEN0
CKS
TXS
RXS/CTS1
DRQ1
TEND1
I/O
O
I

O
I
I/O
I/O
O
I
I
O
IN2
OUT2
There is no buffer connected to the HD64B180.
Ø I/O OUT4
IN2
CPU Clock output
When BUS REQUEST for input is used, an

external clock signal must be supplied.

2 Ø 0 OUT 5 Output with twice the CPU clock

I/O Map

I/O Mapped I/O

Address Input/ Output Bit Description
00 ~ 3F In NORMAL mode, it can be used as user I / O. In TURBO mode, it is used as CPU I/O, so be careful when using it.
40 ~ 7F Reserved for MSX system mode.

RS232C Interface

Address Input/ Output Bit Description
80
81
82



83
84
85
86
87
I/O
I/O
I
I
I
O

I/O
I/O
I/O
O
 
 
bit 0
bit 6
bit 7
bit 0
8251 DATA
8251 STATUS/COMMAND
CD STATUS
8253 CH 2 OUT
CTS STATUS
INT(RXRDY)' CONTROL_'0' interrupt enabled
Unused
8253 CHO
8253 CH 1
8253 CH 2
8253 MODE SET
88~8F MSX System reserved

Printer Interface

Address Input/ Output Bit Description
90
91
I
O
O
bit 1
bit 0
Printer Busy (Busy with '1')
PRINT DATA STROBE ( STROBE with '0')
PRINT DATA
92~97 MSX System reserved

VDP Interface

Address Input/ Output Bit Description
98~9B I/O VDP Control Port
9C~9F MSX System reserved

PSG Interface

Address Input/ Output Bit Description
AO
A1
A2
A3
O
O
I
PSG ADRESS LATCH
PSG DATA WRITE
PSG DATA READ
Cannot be used
A4~A7 MSX System reserved

PPI Interface

Address Input/ Output Bit Description
A8
A9
AA
AB
I/O
I/O
I/O
O
8255 PORT A
8255 PORT b
8255 PORT C
8255 MODE SET
AC~B3 MSX System reserved

Calendar Clock Interface

Address Input/ Output Bit Description
B4
B5
O
I/O
CLOCK ADDRESS LATCH
CLOCK DATA PORT
B6~D7 MSX System reserved

Kanji Rom Interface

Address Input/ Output Bit Description
D8
D9
O
O
I
Lower ADDRESS SET
Higher ADDRESS SET
Kanji DATA READ
DA~F4 MSX System reserved

I/O Control

Address Input/ Output Bit Description
F5 O
O
O
O
bit 0
bit 3
bit 5
bit 7
Kanji ROM
Super Impose
RS-232C
CALENDAR CLOCK
When one of these bits are set to 1, the I/O is no longer available for use.
F6 MSX System reserved

A/V Control

Address Input/ Output Bit Description
F7 O
O
O
I
O
O
O
O
O
bit 0
bit 1
bit 2
bit 3

bit 4
bit 5
bit 6
bit 7
Audio R
Audio L
Video Input Select
Video Input Sense
Sync-Select
AV Control
Ym Control
Ys Control
Video Select
'0' Mixing on
'0' Mixing on
'0' 21PPIND-Sub
'0' No Input
'0' Interval
'0' TV
'0' Off
'0' Super

'0' TV

F8~FF MSX System reserved

Floppy Drive Interface

Address Input/ Output Bit Description
7FF8
7FF9
7FFA
7FFB
I/O
I/O
I/O
I/O
FDC STATUS/COMMAND
FDC TRACK REGISTER
FDC SECTOR REGISTER
FDC DATA REGISTER
7FFC I/O
I/O
I/O
O
I
I/O

I
I
bit 0
bit 1
bit 2
bit 3

bit 4
bit 5
bit 6
bit 7
A DRIVE MOTOR ON/OFF
B DRIVE MOTOR ON/OFF
DRIVE SELECT
SIDE SELECT
SIDE SELECT
DRIVE ENABLE
Cannot be used
FDC DATA REQUEST
FDC INTERRUPT REQUEST
'1' ON
'1' ON
'1' B DRIVE
'1' SIDE 1
'0' SIDE 1
'0' ENABLE

'1' REQUEST
'1' REQUEST

System Control

Address Input/ Output Bit Description
7FFD I/O
I/O
I/O
I/O
I/O
I/O
I
I
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
NMI CONTROL
INT CONTROL
WAIT CONTROL
JVC MODE ACK FLAG
FDC DREQ CONTROL
RS-232C FLAG
TURBO MODE FLAG
JVC MODE FLAG
'0' ENABLE
'1' ENABLE
'0' ENABLE
'1' JVC ACK
'1' ENABLE
'1' ENABLE
'1' TURBO
'0' JVC MODE
INT CONTROL of bit 1 controls the interrupt of mode 2 by using the optional interrupt control board.
By setting JVCACKFLAG of bit 3 to 1, "1" sets the JVCACK signal of the 96 pin bus to '0'.
The bit 5 RS-232C FLAG is a software flag and has no effect on hardware.
7FFE~7FFF MSX System reserved

Note: SLOT 0,1 and SLOT 3 only